/* verilator lint_off UNUSEDSIGNAL */
/* verilator lint_off PINCONNECTEMPTY */
module RISCV_BOARD(
    input               clock,
    input               reset,
    input               io_interrupt,

    input  logic        io_master_awready,
    output logic        io_master_awvalid,
    output logic[31:0]  io_master_awaddr,
    output logic[3:0]   io_master_awid,
    output logic[7:0]   io_master_awlen,
    output logic[2:0]   io_master_awsize,
    output logic[1:0]   io_master_awburst,

    input  logic        io_master_wready,
    output logic        io_master_wvalid,
    output logic[31:0]  io_master_wdata,
    output logic[3:0]   io_master_wstrb,
    output logic        io_master_wlast,
    
    input  logic        io_master_bvalid,
    output logic        io_master_bready,
    input  logic[1:0]   io_master_bresp,
    input  logic[3:0]   io_master_bid,

    input  logic        io_master_arready,
    output logic        io_master_arvalid,
    output logic[31:0]  io_master_araddr,
    output logic[3:0]   io_master_arid,
    output logic[7:0]   io_master_arlen,
    output logic[2:0]   io_master_arsize,
    output logic[1:0]   io_master_arburst,

    input  logic        io_master_rvalid,
    output logic        io_master_rready,
    input  logic[31:0]  io_master_rdata,
    input  logic[1:0]   io_master_rresp,
    input  logic        io_master_rlast,
    input  logic[3:0]   io_master_rid,

    output              io_slave_awready,
    input  logic        io_slave_awvalid,
    input  logic[31:0]  io_slave_awaddr,
    input  logic[3:0]   io_slave_awid,
    input  logic[7:0]   io_slave_awlen,
    input  logic[2:0]   io_slave_awsize,
    input  logic[1:0]   io_slave_awburst,

    output              io_slave_wready,
    input  logic        io_slave_wvalid,
    input  logic[31:0]  io_slave_wdata,
    input  logic[3:0]   io_slave_wstrb,
    input  logic        io_slave_wlast,

    output logic        io_slave_bvalid,
    input  logic        io_slave_bready,
    output logic[1:0]   io_slave_bresp,
    output logic[3:0]   io_slave_bid,

    output              io_slave_arready,
    input  logic        io_slave_arvalid,
    input  logic[31:0]  io_slave_araddr,
    input  logic[3:0]   io_slave_arid,
    input  logic[7:0]   io_slave_arlen,
    input  logic[2:0]   io_slave_arsize,
    input  logic[1:0]   io_slave_arburst,

    output logic        io_slave_rvalid,
    input  logic        io_slave_rready,
    output logic[31:0]  io_slave_rdata,
    output logic[1:0]   io_slave_rresp,
    output logic        io_slave_rlast,
    output logic[3:0]   io_slave_rid

);
wire clk = clock;


// outports wire
wire       	inst_sram_en;
word_t       	inst_sram_addr;
word_t       	data_sram_pc;
wire       	data_sram_en;
wire       	data_sram_wen;
wire [3:0] 	data_sram_mask;
word_t       	data_sram_addr;
word_t       	data_sram_wdata;

RISCV_CPU cpu(
	.clk             	( clk              ),
	.reset           	( reset            ),
	.inst_sram_en    	( inst_sram_en     ),
	.inst_sram_addr  	( inst_sram_addr   ),
	.inst_sram_rdata 	( inst_sram_rdata  ),
	.data_sram_pc    	( data_sram_pc     ),
	.data_sram_en    	( data_sram_en     ),
	.data_sram_wen   	( data_sram_wen    ),
	.data_sram_mask  	( data_sram_mask   ),
	.data_sram_addr  	( data_sram_addr   ),
	.data_sram_wdata 	( data_sram_wdata  ),
	.data_sram_rdata 	( data_sram_rdata  ),
    .axi_inst_flushreq 	( axi_inst_flushreq ),
    .axi_data_flushreq 	( axi_data_flushreq )
);

// outports wire
word_t   	inst_sram_rdata;
wire   	axi_inst_flushreq;
word_t   	debug_pc_i;
wire   	arvalid_i;
word_t   	araddr_i;
wire   	rready_i;
axi_master_read_out_t   	extra_rout_fa;

axi_fetch u_axi_fetch(
	.clk                  	( clk                   ),
	.reset                	( reset                 ),
	.inst_sram_en         	( inst_sram_en          ),
	.debug_inst_pc        	( inst_sram_addr        ),
	.inst_sram_addr       	( inst_sram_addr        ),
	.inst_sram_rdata      	( inst_sram_rdata       ),
	.axi_inst_flushreq 	    ( axi_inst_flushreq     ),
	.debug_pc             	( debug_pc_i            ),
	.arvalid              	( arvalid_i             ),
	.araddr               	( araddr_i              ),
	.arready              	( arready_i             ),
	.rready               	( rready_i              ),
	.rdata                	( rdata_i               ),
	.rresp                	( rresp_i               ),
	.rvalid               	( rvalid_i              ),
    .extra_rin          	( extra_rout_af          ),
	.extra_rout         	( extra_rout_fa         )
);



// outports wire
word_t       	data_sram_rdata;
wire       	axi_data_flushreq;
word_t       	debug_pc;
wire       	arvalid;
word_t       	araddr;
wire       	rready;
wire       	awvalid;
word_t       	awaddr;
wire       	wvalid;
word_t       	wdata;
ysyx_strb_t       	wstrb;
wire       	bready;
axi_master_read_out_t       	extra_rout_lsa;
axi_master_write_out_t       	extra_wout_lsa;

axi_ls u_axi_ls(
	.clk                         	( clk                          ),
	.reset                       	( reset                        ),
	.data_sram_en                	( data_sram_en                 ),
	.debug_data_pc               	( data_sram_pc                 ),
	.data_sram_wen               	( data_sram_wen                ),
	.data_sram_addr              	( data_sram_addr               ),
	.data_sram_mask              	( data_sram_mask               ),
	.data_sram_rdata             	( data_sram_rdata              ),
	.data_sram_wdata             	( data_sram_wdata              ),
    .axi_data_flushreq 	            ( axi_data_flushreq            ),
	.debug_pc                    	( debug_pc                     ),
	.arvalid                     	( arvalid                      ),
	.araddr                      	( araddr                       ),
	.arready                     	( arready                      ),
	.rready                      	( rready                       ),
	.rdata                       	( rdata                        ),
	.rresp                       	( rresp                        ),
	.rvalid                      	( rvalid                       ),
	.awvalid                     	( awvalid                      ),
	.awaddr                      	( awaddr                       ),
	.awready                     	( awready                      ),
	.wvalid                      	( wvalid                       ),
	.wdata                       	( wdata                        ),
	.wstrb                       	( wstrb                        ),
	.wready                      	( wready                       ),
	.bready                      	( bready                       ),
	.bresp                       	( bresp                        ),
	.bvalid                      	( bvalid                       ),
    .extra_rin         	            ( extra_rout_als          ),
	.extra_rout                 	( extra_rout_lsa         ),
	.extra_win                  	( extra_wout_als          ),
	.extra_wout                 	( extra_wout_lsa         )
);




// outports wire
wire        arready_i;
wire        rvalid_i;
word_t rdata_i;
ysyx_resp_t rresp_i;

wire        awready;
wire        wready;
wire        bvalid;
ysyx_resp_t bresp;
wire        arready;
wire        rvalid;
word_t rdata;
ysyx_resp_t rresp;

wire        s_awvalid;
word_t s_awaddr;
wire        s_wvalid;
word_t s_wdata;
ysyx_strb_t s_wstrb;
wire        s_bready;
wire        s_arvalid;
word_t s_araddr;
wire        s_rready;
word_t s_debug_pc;

axi_slave_read_out_t   	extra_rout_af;
axi_slave_write_out_t      extra_wout_af;
axi_slave_read_out_t   	extra_rout_als;
axi_slave_write_out_t   	extra_wout_als;
axi_master_read_out_t   	extra_rout_ax;
axi_master_write_out_t   	extra_wout_ax;

axi_arbiter u_axi_arbiter(
	.clk        	( clk         ),
	.reset      	( reset       ),

    //MASTER 0
    .m0_debug_pc 	( debug_pc_i  ),
	.m0_awvalid 	( `NULL  ),
	.m0_awready 	(   ),
	.m0_awaddr  	(`NULL    ),
	.m0_wvalid  	(`NULL    ),
	.m0_wready  	(    ),
	.m0_wdata   	( `NULL    ),
	.m0_wstrb   	(`NULL     ),
	.m0_bvalid  	(    ),
	.m0_bready  	(`NULL    ),
	.m0_bresp   	(     ),

	.m0_arvalid 	( arvalid_i  ),
	.m0_arready 	( arready_i  ),
	.m0_araddr  	( araddr_i   ),
	.m0_rvalid  	( rvalid_i   ),
	.m0_rready  	( rready_i   ),
	.m0_rdata   	( rdata_i    ),
	.m0_rresp   	( rresp_i    ),

    //MASTER 1
    .m1_debug_pc 	( debug_pc  ),
	.m1_awvalid 	( awvalid  ),
	.m1_awready 	( awready  ),
	.m1_awaddr  	( awaddr   ),
	.m1_wvalid  	( wvalid   ),
	.m1_wready  	( wready   ),
	.m1_wdata   	( wdata    ),
	.m1_wstrb   	( wstrb    ),
	.m1_bvalid  	( bvalid   ),
	.m1_bready  	( bready   ),
	.m1_bresp   	( bresp    ),

	.m1_arvalid 	( arvalid  ),
	.m1_arready 	( arready  ),
	.m1_araddr  	( araddr   ),
	.m1_rvalid  	( rvalid   ),
	.m1_rready  	( rready   ),
	.m1_rdata   	( rdata    ),
	.m1_rresp   	( rresp    ),
    
    //SLAVE
    .s_debug_pc 	( s_debug_pc ),
	.s_awvalid  	( s_awvalid   ),
	.s_awready  	( s_awready   ),
	.s_awaddr   	( s_awaddr    ),
	.s_wvalid   	( s_wvalid    ),
	.s_wready   	( s_wready    ),
	.s_wdata    	( s_wdata     ),
	.s_wstrb    	( s_wstrb     ),
	.s_bvalid   	( s_bvalid    ),
	.s_bready   	( s_bready    ),
	.s_bresp    	( s_bresp     ),

	.s_arvalid  	( s_arvalid   ),
	.s_arready  	( s_arready   ),
	.s_araddr   	( s_araddr    ),
	.s_rvalid   	( s_rvalid    ),
	.s_rready   	( s_rready    ),
	.s_rdata    	( s_rdata     ),
	.s_rresp    	( s_rresp     ),
    
	.m0_extra_rin  	( extra_rout_fa   ),
	.m0_extra_rout 	( extra_rout_af  ),
	.m0_extra_win  	( `NULL   ),
	.m0_extra_wout 	(   ),
	.m1_extra_rin  	( extra_rout_lsa   ),
	.m1_extra_rout 	( extra_rout_als  ),
	.m1_extra_win  	( extra_wout_lsa   ),
	.m1_extra_wout 	( extra_wout_als  ),
	.s_extra_rin   	( extra_rout_xa    ),
	.s_extra_rout  	( extra_rout_ax   ),
	.s_extra_win   	( extra_wout_xa    ),
	.s_extra_wout  	( extra_wout_ax   )
);


// outports wire
wire        s_awready;
wire        s_wready;
wire        s_bvalid;
ysyx_resp_t      s_bresp;
wire        s_arready;
wire        s_rvalid;
word_t      s_rdata;
ysyx_resp_t      s_rresp;

wire        sram_awvalid;
word_t      sram_awaddr;
wire        sram_wvalid;
word_t      sram_wdata;
ysyx_strb_t      sram_wstrb;
wire        sram_bready;
wire        sram_arvalid;
word_t      sram_araddr;
wire        sram_rready;
word_t      sram_debug_pc;

wire        clint_arvalid;
word_t      clint_araddr;
wire        clint_arready;
wire        clint_rready;
word_t      clint_rdata;
ysyx_resp_t      clint_rresp;
wire        clint_rvalid;

wire        amdev_awvalid;
word_t      amdev_awaddr;
wire        amdev_wvalid;
word_t      amdev_wdata;
ysyx_strb_t      amdev_wstrb;
wire        amdev_bready;
wire        amdev_arvalid;
word_t      amdev_araddr;
wire        amdev_rready;
word_t      amdev_debug_pc;

axi_slave_read_out_t   	extra_rout_xa;
axi_slave_write_out_t   extra_wout_xa;
axi_master_read_out_t   extra_rout_xs;
axi_master_write_out_t  extra_wout_xs;


axi_xbar u_axi_xbar(
	.clk          	( clk           ),
	// .reset        	( reset         ),

    .m_debug_pc 	( s_debug_pc    ),
	.m_awvalid    	( s_awvalid     ),
	.m_awready    	( s_awready     ),
	.m_awaddr     	( s_awaddr      ),
	.m_wvalid     	( s_wvalid      ),
	.m_wready     	( s_wready      ),
	.m_wdata      	( s_wdata       ),
	.m_wstrb      	( s_wstrb       ),
	.m_bvalid     	( s_bvalid      ),
	.m_bready     	( s_bready      ),
	.m_bresp      	( s_bresp       ),
	.m_arvalid    	( s_arvalid     ),
	.m_arready    	( s_arready     ),
	.m_araddr     	( s_araddr      ),
	.m_rvalid     	( s_rvalid      ),
	.m_rready     	( s_rready      ),
	.m_rdata      	( s_rdata       ),
	.m_rresp      	( s_rresp       ),

    .sram_debug_pc 	( sram_debug_pc ),
	.sram_awvalid 	( sram_awvalid  ),
	.sram_awready 	( sram_awready  ),
	.sram_awaddr  	( sram_awaddr   ),
	.sram_wvalid  	( sram_wvalid   ),
	.sram_wready  	( sram_wready   ),
	.sram_wdata   	( sram_wdata    ),
	.sram_wstrb   	( sram_wstrb    ),
	.sram_bvalid  	( sram_bvalid   ),
	.sram_bready  	( sram_bready   ),
	.sram_bresp   	( sram_bresp    ),
	.sram_arvalid 	( sram_arvalid  ),
	.sram_arready 	( sram_arready  ),
	.sram_araddr  	( sram_araddr   ),
	.sram_rvalid  	( sram_rvalid   ),
	.sram_rready  	( sram_rready   ),
	.sram_rdata   	( sram_rdata    ),
	.sram_rresp   	( sram_rresp    ),

	.clint_awvalid 	(   ),
	.clint_awready 	(`NULL   ),
	.clint_awaddr  	(    ),
	.clint_wvalid  	(    ),
	.clint_wready  	(`NULL    ),
	.clint_wdata   	(     ),
	.clint_wstrb   	(     ),
	.clint_bvalid  	(`NULL    ),
	.clint_bready  	(    ),
	.clint_bresp   	(`NULL     ),
	.clint_arvalid 	(clint_arvalid  ),
	.clint_arready 	(clint_arready  ),
	.clint_araddr  	(clint_araddr   ),
	.clint_rvalid  	(clint_rvalid   ),
	.clint_rready  	(clint_rready   ),
	.clint_rdata   	(clint_rdata    ),
	.clint_rresp   	(clint_rresp    ),

    .amdev_awvalid 	(amdev_awvalid   ),
	.amdev_awready 	(amdev_awready   ),
	.amdev_awaddr  	(amdev_awaddr    ),
	.amdev_wvalid  	(amdev_wvalid    ),
	.amdev_wready  	(amdev_wready   ),
	.amdev_wdata   	(amdev_wdata     ),
	.amdev_wstrb   	(amdev_wstrb     ),
	.amdev_bvalid  	(amdev_bvalid    ),
	.amdev_bready  	(amdev_bready    ),
	.amdev_bresp   	(amdev_bresp     ),
	.amdev_arvalid 	(amdev_arvalid  ),
	.amdev_arready 	(amdev_arready  ),
	.amdev_araddr  	(amdev_araddr   ),
	.amdev_rvalid  	(amdev_rvalid   ),
	.amdev_rready  	(amdev_rready   ),
	.amdev_rdata   	(amdev_rdata    ),
	.amdev_rresp   	(amdev_rresp    ),

	.m_extra_rin     	( extra_rout_ax      ),
	.m_extra_rout    	( extra_rout_xa     ),
	.m_extra_win     	( extra_wout_ax      ),
	.m_extra_wout    	( extra_wout_xa     ),
	.sram_extra_rin  	( extra_rout_sx   ),
	.sram_extra_rout 	( extra_rout_xs  ),
	.sram_extra_win  	( extra_wout_sx   ),
	.sram_extra_wout 	( extra_wout_xs  )
);


// outports wire
wire   	clint_arready;
wire   	clint_rdata;
wire   	clint_rresp;
wire   	clint_rvalid;

axi_clint u_axi_clint(
	.reset    	( reset     ),
	.clk      	( clk       ),
	.arvalid  	( clint_arvalid   ),
	.araddr   	( clint_araddr    ),
	.arready  	( clint_arready   ),
	.rready   	( clint_rready    ),
	.rdata    	( clint_rdata     ),
	.rresp    	( clint_rresp     ),
	.rvalid   	( clint_rvalid    )
);


wire   	sram_arready;
word_t   	sram_rdata;
ysyx_resp_t   	sram_rresp;
wire   	sram_rvalid;
wire   	sram_awready;
wire   	sram_wready;
ysyx_resp_t   	sram_bresp;
wire   	sram_bvalid;
axi_slave_read_out_t   	extra_rout_sx;
axi_slave_write_out_t   extra_wout_sx;
assign sram_awready = io_master_awready;
assign io_master_awvalid = sram_awvalid;
assign io_master_awaddr = sram_awaddr;
assign io_master_awid = extra_wout_xs.awid;
assign io_master_awlen = extra_wout_xs.awlen;
assign io_master_awsize = extra_wout_xs.awsize;
assign io_master_awburst = extra_wout_xs.awburst;

assign sram_wready = io_master_wready;
assign io_master_wvalid = sram_wvalid;
assign io_master_wdata = sram_wdata;
assign io_master_wstrb = sram_wstrb;
assign io_master_wlast = extra_wout_xs.wlast;

assign io_master_bready = sram_bready;
assign sram_bvalid = io_master_bvalid;
assign sram_bresp = io_master_bresp;
assign extra_wout_sx.bid = io_master_bid;

assign sram_arready = io_master_arready;
assign io_master_arvalid = sram_arvalid;
assign io_master_araddr = sram_araddr;
assign io_master_arid = extra_rout_xs.arid;
assign io_master_arlen = extra_rout_xs.arlen;
assign io_master_arsize = extra_rout_xs.arsize;
assign io_master_arburst = extra_rout_xs.arburst;

assign io_master_rready = sram_rready;
assign sram_rvalid = io_master_rvalid;
assign sram_rdata = io_master_rdata;
assign sram_rresp = io_master_rresp;
assign extra_rout_sx.rlast = io_master_rlast;
assign extra_rout_sx.rid = io_master_rid;



// outports wire
wire   	amdev_arready;
word_t   	amdev_rdata;
ysyx_resp_t   	amdev_rresp;
wire   	amdev_rvalid;
wire   	amdev_awready;
wire   	amdev_wready;
ysyx_resp_t   	amdev_bresp;
wire   	amdev_bvalid;

// axi_slave_read_out_t   	extra_rout_sx;
// axi_slave_write_out_t   extra_wout_sx;

axi_amdev u_axi_amdev(
	.reset    	( reset     ),
	.clk      	( clk       ),
	.debug_pc 	( s_debug_pc  ),
	.arvalid  	( amdev_arvalid   ),
	.araddr   	( amdev_araddr    ),
	.arready  	( amdev_arready   ),
	.rready   	( amdev_rready    ),
	.rdata    	( amdev_rdata     ),
	.rresp    	( amdev_rresp     ),
	.rvalid   	( amdev_rvalid    ),

	.awvalid  	( amdev_awvalid   ),
	.awaddr   	( amdev_awaddr    ),
	.awready  	( amdev_awready   ),
	.wvalid   	( amdev_wvalid    ),
	.wdata    	( amdev_wdata     ),
	.wstrb    	( amdev_wstrb     ),
	.wready   	( amdev_wready    ),
	.bready   	( amdev_bready    ),
	.bresp    	( amdev_bresp     ),
	.bvalid   	( amdev_bvalid    )


	// .m_extra_rin  	( extra_rout_xs   ),
	// .m_extra_rout 	( extra_rout_sx  ),
	// .m_extra_win  	( extra_wout_xs   ),
	// .m_extra_wout 	( extra_wout_sx  )
);


// outports wire
// wire   	arready_i;
// word_t   	rdata_i;
// ysyx_resp_t   	rresp_i;
// wire   	rvalid_i;

// axi_inst_ram u_axi_inst_ram(
// 	.reset    	( reset       ),
// 	.clk      	( clk         ),
// 	.debug_pc 	( debug_pc_i  ),
// 	.arvalid  	( arvalid_i   ),
// 	.araddr   	( araddr_i    ),
// 	.arready  	( arready_i   ),
// 	.rready   	( rready_i    ),
// 	.rdata    	( rdata_i     ),
// 	.rresp    	( rresp_i     ),
// 	.rvalid   	( rvalid_i    )
// );


// outports wire
// wire   	arready;
// word_t   	rdata;
// ysyx_resp_t   	rresp;
// wire   	rvalid;
// wire   	awready;
// wire   	wready;
// ysyx_resp_t   	bresp;
// wire   	bvalid;

// axi_data_ram u_axi_data_ram(
// 	.reset    	( reset     ),
// 	.clk      	( clk       ),
// 	.debug_pc 	( debug_pc  ),
// 	.arvalid  	( arvalid   ),
// 	.araddr   	( araddr    ),
// 	.arready  	( arready   ),
// 	.rready   	( rready    ),
// 	.rdata    	( rdata     ),
// 	.rresp    	( rresp     ),
// 	.rvalid   	( rvalid    ),
// 	.awvalid  	( awvalid   ),
// 	.awaddr   	( awaddr    ),
// 	.awready  	( awready   ),
// 	.wvalid   	( wvalid    ),
// 	.wdata    	( wdata     ),
// 	.wstrb    	( wstrb     ),
// 	.wready   	( wready    ),
// 	.bready   	( bready    ),
// 	.bresp    	( bresp     ),
// 	.bvalid   	( bvalid    )
// );



// // outports wire
// word_t       	data_sram_rdata;

// DATA_SRAM u_DATA_SRAM(
// 	.reset           	( reset            ),
// 	.clk             	( clk              ),
// 	.data_sram_pc    	( data_sram_pc     ),
// 	.data_sram_en    	( data_sram_en     ),
// 	.data_sram_wen   	( data_sram_wen    ),
// 	.data_sram_mask  	( data_sram_mask   ),
// 	.data_sram_addr  	( data_sram_addr   ),
// 	.data_sram_wdata 	( data_sram_wdata  ),
// 	.data_sram_rdata 	( data_sram_rdata  )
// );


// // outports wire
// word_t   	inst_sram_rdata;

// INST_SRAM u_INST_SRAM(
// 	.clk             	( clk              ),
// 	.reset           	( reset            ),
// 	.inst_sram_en    	( inst_sram_en     ),
// 	.inst_sram_addr  	( inst_sram_addr   ),
// 	.inst_sram_rdata 	( inst_sram_rdata  )
// );


endmodule
